Banker

ID 64353400023
latest available version (1.0)
compatible with ARTIQ
source available

Banker is a versatile EEM module with 128 GPIOs managed by ICE40HX8K-CT256 FPGA allowing complete customization. Every channel can be configured either as 3.3 V or 5 V voltage level. The former one allows to drive 50R load. The FPGA configuration may be changed using on-board FLASH via I2C or using local SPI connector.

There are many interfaces allowable:

  • 8 x 8 channel IDC connectors
  • 2 x 32 channael VHDCI connectors
  • 2 downstream EEM connectors for daisy-chain connections of several Banker modules.

The flexibility allows to cover variety of applications listed here.

The 12 V power supply may be provided via DC Jack or Molex connector.

Main features

  • 128 channel GPIO module
  • different communication interfaces
  • daisy-chain connection available
  • SPI Flash for FPGA configuration
  • 3.3 V or 5 V output levels

Software support

  • Flashing via I2C implemented

Documentation

GitHub wiki
Link
Banker description on GitHub wiki

Resources

GitHub Repository
Link
GitHub repository containing Banker's source files
Flashing via I2C
Link
Gateware to configure Banker via I2C using Kasli

Applications

  • Controlling many TTL channels with single EEM slot
  • Simple remote LVDS IO with VHDCI cable
  • A basic gateware approach would implement each port of eight signals as a group of SPI addressable registers (direction, input, output, clear output, set output). Maybe with double buffering and some latching operation that synchronizes changes across banks
  • Programmable logic router for photon coincidence detection and large matrix photon correlation, higher order correlator
  • Simple photon counter, TDC, start-stop counter, high-res TDC with any of the available techniques (wave union etc)
  • Large array SPI router/multiplexer. 16 SPI independent buses with 5 chip selects each. Or 32 independent SPI buses.
  • Interlock logic router, supervisor, watchdog
Paweł Kozakiewicz
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